This invention relates to a solid-state imaging device which utilizes static induction transistors (hereinafter referred to as SIT) and which generates no spurious signals even when the incident quantity of light is saturated or almost saturated.
Conventional solid-state imaging devices generally utilize MOS transistors or charge coupled devices such as CCDs or BBDs. Solid-state imaging devices utilizing MOS transistors can only generate faint output signals. Besides, they exhibit an inadequate S/N ratio and a poor photosensitivity. Those utilizing CCDs, BBDs, etc. involve charge loss at the time of charge transfer, and are rather difficult to manufacture.
In view of these problems, solid-state imaging devices utiilizing a static induction transistor for each pixel have been proposed, as disclosed, for example, in Japanese Patent Laid-Open No. 105672/1983. An example of such devices will be described with reference to FIGS. 1A and 1B.
FIG. 1A is a perspective view showing the structure of a pixel in a solid-state imaging device using SITs, and FIG. 1B is a circuit diagram of the solid-state imaging device.
Reference numeral 1 in FIG. 1A denotes an n.sup.+ silicon substrate which acts as the drain of the SIT. This substrate 1 is piled with an n.sup.- epitaxial layer 2 which serves as the channel area. A shallow n.sup.+ source area 3 is formed in this epitaxial layer 2, and is surrounded by a p.sup.+ gate area 4 provided in the epitaxial layer 2. Formed on the gate area 4 is an MOS capacitor 5, through which pulses are supplied.
When the gate area 4 is inversely biased, a depletion layer is formed outside this gate area 4. When hole-electron couples are generated by light impinging upon this depletion layer, the electrons are swept away to the source area 3 and the drain area 1, the holes being accumulated in the gate area 4. This causes the gate potential to be raised, resulting in the electric current between the drain and the source being modulated, whereby a signal amplified by the light is obtained. Reference numeral 6 in FIG. 1A denotes a separation area which serves to separate the pixels from each other.
Reference numerals 10-11, 10-12, . . . . . 10-21, 10-22, . . . . . , . . . . . , 10-44 in FIG. 1B denote SITs, each of which forms a pixel as is shown in FIG. 1A. In order to simplify the explanation, the SITs are shown here as arranged in four rows and four columns. The sources of the SITs belonging to the same longitudinal line are commonly connected to one of vertical signal lines 11-1, 11-2, . . . . . 11-4, which are connected to a video line 14 through respective switching MOSFETs 13-1, 13-2, . . . . . 13-4 composing the horizontal selection switches. The gates of the switching MOSFETs 13-1, . . . . 13-4 are connected to a horizontal scanning circuit 15, and horizontal pulses .phi..sub.S1, .phi..sub.S2, . . . . .phi..sub.S4 are applied to the gates of these MOSFETs.
The gates of the SITs belonging to the same lateral line, on the other hand, are commonly connected to one of row lines 12-1, 12-2, . . . . . 12-4. These row lines 12-1, 12-2, . . . . . 12-4 are connected to a vertical scanning circuit 16, vertical scanning pulses .phi..sub.G1, .phi..sub.G2, . . . . . .phi..sub.G4 being applied to the gates of the SITs through the respective row lines mentioned above.
When one of the above-mentioned vertical scanning pulses is applied to a certain row line to select a pixel row and one of the above-mentioned horizotal scanning pulses is applied to a certain vertical signal line to select a pixel column, the optical signal current of the pixel at the intersection is read out. By thus successively outputting the horizontal and vertical scanning pulses, the pixels are successively scanned, whereby the signals for one picture are obtained.
FIG. 2 is a signal waveform diagram showing the timing of the pulses for operating the above-described solid-state imaging device. The vertical scanning pulses .phi..sub.G for selecting gates consist of pulses having two different high levels V.sub.RD and V.sub.RS. During the horizontal scanning period t.sub.H of each row line, the pulses exhibit the read-out level V.sub.RD, and during the subsequent horizontal blanking period t.sub.BL, they exhibit the reset level V.sub.RS. The horizontal scanning pulses .phi..sub.S for selecting sources reach the high level during each horizontal scanning period, thus successively scanning pixels arranged laterally. The resetting pulse .phi..sub.R reaches the high level during each horizontal blanking period t.sub.BL, thus resetting pixels whose signals have been read out.
FIG. 3 shows the circuit construction of a pixel SIT T.sub.P including parasitic capacitance C.sub.GD between the gate and the drain, parasitic capacitance C.sub.GS between the gate and the source, floating capacitance C.sub.S of the source line, and ON resistance R.sub.ON of the switching MOSFET T.sub.S for horizontal selection. Reference character T.sub.R denotes the MOSFET for resetting.
FIG. 4 shows the temporal changes in the gate potential V.sub.G and the source potential V.sub.S of a pixel SIT when a horizontal scanning pulse .phi..sub.S, a vertical scanning pulse .phi..sub.G and a resetting pulse .phi..sub.R are applied thereto. Reference character .phi..sub.B denotes the forward threshold voltage of a gate-source diode which will be described later.
The temporal changes in the gate potential V.sub.G and the source potential V.sub.S will be described with reference to FIGS. 2 to 4.
(1) At the time t.sub.1 :
.phi..sub.G =V.sub.RS (&gt;.phi..sub.B). When the resetting pulse .phi..sub.R has reached the High level, the source potential V.sub.S is reset to the GND, so that V.sub.G =.phi..sub.B.
(2) At the time t.sub.2 :
When the pulses .phi..sub.G and .phi..sub.R are set to the GND, the gate potential V.sub.G is put in an inversely biased condition which is given by the following equation (1) and starts optical integration. EQU V.sub.G (t.sub.2)=-C.sub.G /(C.sub.G +C.sub.J) V.sub.RS +.phi..sub.B ( 1)
where C.sub.J =C.sub.GS +C.sub.GD
(3) At the time t.sub.3 :
During the optical integration time, the optical charge Q.sub.Ph generated by the irradiation of light is accumulated in the gate capacitance (C.sub.G +C.sub.J).
The above Q.sub.Ph is given by the following equation (2): ##EQU1## where G.sub.L =ratio of generation (.mu.A/.mu.W); A=light receiving area (cm.sup.2); P=light irradiance (.mu.W/cm.sup.2); t.sub.int =integration time (S): and E=exposure (E=P.multidot.t.sub.int). The gate potential V.sub.G is given by the following equation (3), which is obtained from the above equations (1) and (2). EQU V.sub.G (t.sub.3)=-C.sub.G /(C.sub.g +C.sub.J).multidot.V.sub.RS +.phi..sub.B +Q.sub.PH /(C.sub.G +C.sub.J) (3)
(4) At the time t.sub.4 :
When .phi..sub.G =V.sub.RD, the gate potential V.sub.G becomes as follows: ##EQU2##
When V.sub.G (t.sub.4)&gt;V.sub.P, the drain current of the pixel SIT flows, charging the source line capacitance C.sub.S. Here, V.sub.P denotes the potential difference between the gate and the source which causes the drain current of the pixel SIT to flow, and is called pinch-off voltage. This charging is continued until the potential difference V.sub.GS between the gate and the source becomes V.sub.P. The source potential is consequently given by the following equation (5): EQU V.sub.S (t.sub.4)=C.sub.G /(C.sub.G +C.sub.J).multidot.(V.sub.RD -V.sub.RS) +.phi..sub.B +Q.sub.Ph /(C.sub.G +C.sub.J)-V.sub.P ( 5)
Since V.sub.P &lt;.phi..sub.B, almost no current flows from the p.sup.+ gate to the n.sup.+ source of the pixel SIT.
(5) At the time t.sub.5 :
The horizontal selection pulse .phi..sub.S reaches the High level, the source line being connected to the load resistor R.sub.L through the switching MOSFET T.sub.S (the ON resistance is R.sub.ON). The output V.sub.OUT changes with time and is given by the following equation (6): EQU V.sub.OUT (t)=R.sub.L /(R.sub.ON +R.sub.L).multidot.V.sub.S (t) (6)
FIG. 5 shows the temporal changes of the gate potential V.sub.G, the source potential V.sub.S and the output V.sub.OUT when the horizontal selection pulse .phi..sub.S has reached the High level. When in FIG. 5 the horizontal selection pulse .phi..sub.S has reached the High level, the p.sup.+ gate and the n.sup.+ source of the pixel SIT are put in the forward direction and pn diode current flows, the signal charge accumulated in the gate capacitance flowing out to the source. The optical signal charge in this solid-state imaging device is consequently destroyed, the gate potential V.sub.G and the source potential V.sub.S being both decreased. The value of the output V.sub.OUT given by the above equation (6) becomes smaller than the value when the above equation (5) is substituted into V.sub.S (t) in the equation (6).
FIG. 6 shows the circuit construction of another example of the solid-state imaging device proposed by the applicant in U.S. Pat. Appln. No. 07/66424. In this example, the sources of drive MOSFETs 18-1, 18-2, . . . . 18-4 are connected to the respective drains of switching MOSFETs 13-1, 13-2. . . . . 13-4 which constitute the horizontal selection switches. The gates of these drive MOSFETs are connected to the respective vertical signal lines 11-1, 11-2, . . . . 11-4. The drains are commonly connected to a power source V.sub.DD and a video line resetting MOSFET 19 is connected to a video line 14, parallel to a load resistor R.sub.L. The rest of the circuit construction is the same as that shown in FIG. 1B.
In this solid-state imaging device, a video line resetting pulse .phi..sub.RV shown in FIG. 7 is applied to the gate of the resetting MOSFET 19 and the drive pulses shown in FIG. 2 are applied to the corresponding elements, whereby the device is operated in the same manner as the solid-state imaging device shown in FIG. 1B. Further, this solid-state imaging device is capable of taking out an output in proportion to its optical signal charge during each subsequent readout period, without destroying the optical signal charge accumulated in the gate capacitance of the pixel SITs.
Here, the output voltage V.sub.OUT when this solid-state imaging device is operated with the drive pulses shown in FIG. 2 is expressed by the following equation (7): EQU V.sub.OUT =a{V.sub.S (t.sub.4)-V.sub.T } (7)
The reference character V.sub.T denotes the threshold voltage of the drive MOSFETs 18-1, 18-2, . . . . 18-4, and the reference character a denotes the voltage gain of the source follower formed by the drive MOSFETs 18-1, 18-2, . . . . 18-4, the switching MOSFETs 13-1, 13-2, . . . . 13-4 and the load resistor R.sub.L. By substituting the above equation (5) into this equation (7), the following equation (8) is obtained: EQU V.sub.OUT =a{C.sub.G /(C.sub.G +C.sub.J).multidot.(V.sub.RD -V.sub.RS)+.phi..sub.B +Q.sub.Ph /(C.sub.G +C.sub.J)-V.sub.P -V.sub.T }(8)
As will be appreciated from the above equation (7), no output appears in this solid-state imaging device until the source potential V.sub.S has become equal to or higher than the threshold voltage V.sub.T. The values of the V.sub.RD and V.sub.RS in this solid-state imaging device are accordingly so set that V.sub.OUT .gtoreq.0 when the selected pixel is in the dark condition (Q.sub.Ph =0).
While the above-described imaging device is capable of effectively overcoming the problems in those solid-state imaging devices using MOS transistors, CCDs, BBDs or the like, various experiments conducted by the inventors of the present invention has revealed that it exhibits a poor blooming resistance. The term "blooming" will now be explained.
When intensive light in excess of the saturated quantity of light impinges upon a non-selected pixel SIT of the solid-state imaging device shown in FIG. 1B, causing the gate potential thereof to reach the pinch-off voltage V.sub.P, this non-selected pixel SIT is turned ON and a channel current (drain/source current) flows, thereby raising the potential of the vertical signal line to which this SIT is connected. When in this condition another pixel SIT which is connected to the same vertical signal line is selected, the output of the above non-selected pixel SIT appears at the end of the load resistor R.sub.L together with the inherent output of that selected pixel SIT. As a result, a blooming in the form of white vertical stripes are observed on the TV monitor.
Here, consideration will be given to the quantity of light required for raising the gate potential of the non-selected pixel SIT up to the pinch-off voltage V.sub.P. Suppose in FIG. 1B only the pixel SIT 10-33 is irradiated with light and the other pixel SITs are not irradiated with light, the quantity of light which causes the output to appear when the pixel SIT 10-23 is selected may be obtained as shown in FIG. 8. To simplify the description, it will be assumed here that non-interlace scanning is to be conducted. Since output saturation is generated through application of the resetting pulse .phi..sub.R to the horizontal blanking time t.sub.BL and clamping of the gate voltage V.sub.G by .phi..sub.B, the rate of change m.sub.sat (the gradient of the virtual straight lines in FIG. 8) of the gate potential V.sub.G corresponding to the saturated light quantity can be expressed by the following equation (9): EQU m.sub.sat ={C.sub.G .multidot.V.sub.RS /(C.sub.G +C.sub.J)}/{T.sub.f -(t.sub.H +t.sub.BL)} (9)
where T.sub.f denotes the field time.
When on the other hand the pixel SIT 10-23 is selected, the rate of change m,(the gradient of the full straight lines in FIG. 8) of the gate voltage V.sub.G10-33 of the pixel SIT 10-33 corresponding to the quantity of light which causes the false output of the pixel SIT 10-33 to appear can be expressed by the following equation (10), supposing that the pixel SIT 10-33 is the third one in the column direction, and that the alias appears with a timing corresponding to the pixel readout timinig for the row line prior to that of the proper pixel concerned. EQU m'={C.sub.G .multidot.V.sub.RS /(C.sub.G +C.sub.J)-.phi..sub.B +V.sub.P }/{T.sub.f -(t.sub.H +t.sub.BL)+3t.sub.S } (10)
where t.sub.S denotes the period of the horizontal scanning pulse in the horizontal scanning circuit 15.
As will be appreciated from FIG. 8 and the equations (9), (10), m.sub.sat &gt;m'. This implies that the quantity of light which causes the alias to appear when the pixel SIT 10-23 is selected is smaller than the saturated quantity of light. Actually, a quantity of light several times larger than the saturated quantity of light will be necessary for the white vertical stripes to be observed on the TV monitor. At all events, it may be concluded that the device exhibits a very low blooming resistance.
Next, the blooming generation in the solid-state imaging device shown in FIG. 6 will be described. FIG. 9 depicts a situation in which, as in the above described case, the output of the pixel SIT 10-33 appears when the pixel SIT 10-23 is selected, with exclusively the pixel SIT 10-33 being irradiated with light. Here, the rate of change m" (the gradient of the full straight lines in FIG. 9) of the gate potential V.sub.G10-33 corresponding to the quantity of light which causes the alias of the pixel SIT 10-33 to appear may be expressed, as in the above case, by the following equation (11): EQU m"=(V.sub.T +V.sub.P -.phi..sub.B)/3t.sub.s ( 11)
In other words, this solid-state imaging device exhibits blooming resistance until the quantity of light reaches the value m"/m.sub.sat times larger than the saturated quantity of light. The reason for this result is that an additional quantity of light is required in order to raise the gate potential V.sub.G10-33 by the amount corresponding to V.sub.T, which is not the case with the solid-state imaging device shown in FIG. 1B. In a prototype device built by the inventor, V.sub.T =0.8 (V), V.sub.P =0.3 (V), .phi.=0.8 (V), C.sub.G /(C.sub.G +C.sub.J)=0.6, and V.sub.RS =3 (V). The blooming reistance m"/m.sub.sat of this device is: ##EQU3##
This value corresponds to the requisite quantity of light for the the alias to appear at the right end of the TV monitor. Actually, a still larger quantity of light is necessary for the alias to be observed as white stripes. However, even this is not to be regared as a sufficient blooming resistance.